1. Field of the Invention
The present invention relates to scan path circuits and, more specifically, to a scan path timing optimizing apparatus determining connection order of scan path circuits to realize optimum signal timings.
2. Description of the Background Art
Recently, along with ever increasing speed of operation and higher degree of integration of semiconductor circuits, it has become more and more common to provide a built-in, scanning type test circuits. Conventional scanning type test circuits utilize, as methods of determining order of connection of scan path circuits, a method in which the order of connection of scan terminals of sequential circuits (hereinafter referred generally as FFs), including a flip-flop circuit, a latch circuit or an IP (intellectual property) constituting the scan path circuits, is determined without considering placement information of the scan path circuits, and a method in which the order of connection of scan terminals of FFs is determined considering placement information of the scan path circuits.
Japanese Patent Laying-Open No. 10-335471 discloses one technique related to the method in which the orders of connection of scan terminals of FF is determined considering placement information of the scan path circuits. In the method of interconnecting a scan path network disclosed in Japanese Patent Laying-Open No. 10-335471, placement and design of standard cells and the like are performed based on circuit information of an LSI (Large Scale Integrated circuit), for example, and clock path delay time of each FF in the LSI is estimated by a clock delay calculating process. By a skew estimating process, clock skew between each FF is calculated.
Further, distance between each FF is calculated by a distance calculating process. By a path selection process, order of connection between each FF is determined considering not only the distance but also the clock skew. Thus, possibility of hold time errors is reduced.
The above-described method in which the order of connection of scan terminals of FFs is determined without considering placement information of the scan path circuits, however, is problematic, as interconnections between cells including the scan path circuits become congested, possibly resulting in unmanageable interconnection.
In the method in which the order of connection of scan terminals of FFs is determined considering placement information of the scan path circuits, the order of connection is determined to make shortest the interconnections between scan terminals of the FFs. Therefore, data transfer time may possibly be too short, resulting in a hold time error. Here, it becomes necessary to improve timings by inserting buffers between scan terminals, so as to avoid the hold time error. When the number of hold time errors is large, however, the number of buffers would be too much increased, making cell placement or interconnection impossible.
In the method of interconnecting a scan path network disclosed in Japanese Patent Laying-Open No. 10-335471, order of connection between each FF is determined considering not only the distance but also the clock skew. This means that every distance and every clock skew between each FF must be calculated, and therefore, it is difficult to quickly determine the order of connection between each FF.